The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a structure and method for improved field emitter arrays.
Recent years have seen an increased interest in field emitter displays. This is attributable to the fact that such displays can fulfill the goal of consumer affordable hang-on-the-wall flat panel television displays with diagonals in the range of 20 to 60 inches. Certain field emitter displays, or flat panel displays, operate on the same physical principle as fluorescent lamps. A gas discharge generates ultraviolet light which excites a phosphor layer that fluoresces visible light. Other field emitter displays operate on the same physical principals as cathode ray tube (CRT) based displays. Excited electrons are guided to a phosphor target to create a display. Silicon based field emitter arrays are one source for creating similar displays.
Single crystalline structures have been under investigation for some time. However, large area, TV size, displays are likely to be expensive and difficult to manufacture from single crystal silicon wafers. Polycrystalline silicon, on the other hand, provides a viable substitute to single crystal silicon since it can be deposited over large areas on glass or other substrates.
Polysilicon field emitter devices have been previously described for flat panel field emission displays. But such field emitters have only been produced according to lengthy, conventional, integrated circuit technology, e.g., by masking polysilicon and then either etching or oxidation to produce cones of polysilicon with points for field emitters. The cones of polysilicon can then be utilized directly or undergo further processing to cover the points with some inert metal or low work function material.
Thus, it is desirable to develop a method and structure for large population density arrays of field emitters without compromising the responsiveness and reliability of the emitter. Likewise, it is desirable to obtain this result through an improved and streamlined manufacturing technique.
The above mentioned problems with field emitter arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a field emitter device on a substrate. The field emitter device includes a cathode formed in a cathode region of the substrate. A gate insulator is formed in an insulator region of the substrate. The gate insulator and the cathode are formed from a single layer of polysilicon by using a self-aligned technique. A gate is formed on the gate insulator. Further, an anode opposes the cathode.
In another embodiment, a field emitter device on a substrate is provided. The device includes a cathode formed in a cathode region of the substrate. The cathode consists of a polysilicon cone. A porous oxide layer is formed in an insulator region of the substrate. The porous oxide layer and the polysilicon cone are formed from a single layer of polysilicon by using a self-aligned technique. A gate is formed on the porous oxide layer. Further, the gate and the polysilicon cone are formed using the self-aligned technique. An anode opposes the cathode.
In another embodiment of the present invention, a field emitter array is provided. The array includes a number of cathodes which are formed in rows along a substrate. A gate insulator is formed along the substrate and surrounds the cathodes. The gate insulator material and the cathodes are formed from a single layer of polysilicon by using a self-aligned technique. A number of gate lines are formed on the gate insulator. Further, a number of anodes are formed in columns orthogonal to and opposing the rows of cathodes.
In another embodiment of the present invention, a flat panel display is provided. The flat panel display includes a field emitter array formed on a glass substrate. The field emitter array includes a number of cathodes formed in rows along the substrate. The number of cathodes are formed of polysilicon cones. A gate insulator is formed along the substrate and surrounds the cathodes. The gate insulator material and the cathodes are formed from a single layer of polysilicon by using a self-aligned technique. A number of gate lines formed on the gate insulator. Further the array has a number of anodes formed in columns orthogonal to, and opposing, the rows of cathodes. The anodes include multiple phosphors, and the intersection of the rows and columns form pixels. Further, the display includes a row decoder and a column decoder each coupled to the field emitter array in order to selectively access the pixels. A processor is included which is adapted to receiving input signals and providing the input signals to the row and column decoders in order to access the pixels.
In another embodiment, a method for forming a field emitter device on a substrate is provided. The method includes forming a polysilicon cone on the substrate. A porous oxide layer is formed on the substrate. The method includes forming the porous oxide layer and the polysilicon cone from a single layer of polysilicon using a self-aligned technique. A gate layer is formed on the porous oxide layer. Further, the polysilicon cone is isolated from the gate. And, an anode is formed opposite the cathode.
Thus, an improved method and structure are provided for simultaneously fabricating polysilicon cones for a field emitter and a porous insulating oxide layer for supporting a gate material. The porous insulating oxide is fabricated by first making the polysilicon porous in the field regions by an anodic etch and then oxidation. This is a fully self-aligned process and only one masking is used. Shaping of the gate material in close proximity to the top of the cone is achieved by a lift-off technique and requires no special deposition techniques like depositions at a grazing incidence to improve the emitter shape.